System for storing device test information on a semiconductor device using on-device logic for determination of test results

ABSTRACT

A system for testing a semiconductor device and storing device test results in nonvolatile memory elements on the tested device, in which the semiconductor device includes logic circuitry which allows test results to be determined on the device. Test results are stored temporarily in one or more latch elements on the semiconductor device and are subsequently stored in nonvolatile memory elements. The invention eliminates the need for device testing equipment to perform a determination of test results and thus may simplify the design of test equipment. In one embodiment of the invention, passing test results are stored in a mixed code of set and unset nonvolatile memory elements such that the test results contain information about correct application of test signals as well as correct functioning of the semiconductor device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/794,696,filed Mar. 5, 2004, pending, which is a continuation of application Ser.No. 09/651,858, filed Aug. 30, 2000, now U.S. Pat. No. 6,829,737, issuedDec. 7, 2004.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to integrated circuit test circuits andmethods. In particular, the present invention relates to storage of testresult data on an integrated circuit device in nonvolatile memoryelements and, most particularly, to the inclusion of logic in theintegrated circuit device for determining the results of device testsand enabling the storage of test results in the nonvolatile memoryelements.

2. Statement of the Art

Semiconductor integrated circuit devices are manufactured on wafers orother substrates of semiconductor material. Conventionally, many devicesare manufactured on a single wafer and individual devices or groups ofdevices are cut from the wafer and packaged. The devices are tested atvarious points during the manufacturing process, e.g., with electricalprobes while they are still on the wafer, in die form (after singulationbut prior to packaging) and after packaging.

During testing, a particular signal or combination of signals is inputto the device and the output value or values read from the device arecompared with values expected to be obtained from a properly functioningdevice. Tests may involve a particular signal or combination of signalsbeing delivered repetitively, perhaps under extreme environmentalconditions (temperature, voltage, etc.) in order to identify a devicewhich would fail after a shorter than usual period of use (“burn-in”testing). Other tests may involve a number of different signals orsignal combinations delivered in sequence. One method for testing amemory device is to deliver the same signal/signal combination tomultiple identical subsections of the device simultaneously and comparethe values read from the subsections (“compression testing”). If all ofthe respective, read values match, the test has been passed, while amismatch between respective values read from any of the subsectionsindicates a device malfunction and failure of the test.

A particular test or test sequence often includes multiple test steps.Moreover, a complete test flow will often require that devices move fromone piece of test equipment to another. For example, a first piece oftest equipment and test fixtures may be utilized for probe testing,another for burn-in testing and yet another for packaged device testingafter burn-in.

After a particular test or test sequence has been completed, deviceswhich have failed some or all of a test may be separated from the gooddevices. However, a device which has failed one portion of the testsequence may pass subsequent test sequences, so if it is erroneouslyplaced into the “good” bin and then passes subsequent tests it mayeventually be classified and sold as fully functional. One way to avoidthis type of error is to store information regarding the test history ofthe device on the device itself in nonvolatile memory elements. Oneexample describing storage of test results in nonvolatile memory on asemiconductor device is co-pending U.S. patent application Ser. No.08/946,027, the disclosure of which is hereby incorporated herein byreference.

Test equipment used for testing integrated circuit devicesconventionally transmits a test signal and then receives an outputsignal from the integrated circuit device. The test equipment thencompares the output signal from the integrated circuit device with thevalue expected to be obtained from a properly functioning device andsends an instruction to the device which causes a specific nonvolatilememory element to be set to indicate either pass or fail of the teststep. A series of nonvolatile memory elements may be set to indicate theresults of a series of tests or test steps. The tester thus must includedetectors and comparators so that it can read the output signal andperform a comparison to determine passage or failure of the test.

It would be advantageous to decrease the cost and complexity of thetester by eliminating the need for detectors and comparators on the testequipment.

It would be advantageous to eliminate the need for intelligence indevice test equipment, by instead placing intelligence on the devicebeing tested.

It would be desirable to provide for the storage of informationconcerning correct application of test sequences to the device on thedevice itself.

These and other advantages are provided by the invention.

BRIEF SUMMARY OF THE INVENTION

The present invention includes a method and system for storingsemiconductor device test results on a tested device, using on-devicetest circuitry for the determination of test results and control of testresult storage. The semiconductor device, which may be a memory device,a microprocessor, or other semiconductor device, includes a plurality ofnonvolatile memory elements which are set to indicate the results of aseries of multiple tests or test steps. The semiconductor device mayalso include comparator circuitry, which compares test signals sent tothe semiconductor device from a tester with data values read from thesemiconductor device following receipt of the test signals, or whichperforms a comparison between data values read from multiple regions ofa device, to determine correct functioning of the device. Thesemiconductor device includes a latch which is set to indicate passageor failure of the test. The latch enables circuitry which causes anonvolatile memory element to be set upon receipt of an instruction fromthe tester. The latch, and subsequently the nonvolatile memory element,is set to represent the test results according to a predetermined rule.Typically, one logic level is latched to represent passage of a test andanother is used to represent failure of the test. For example, logichigh could represent pass and logic low would then represent fail or,alternatively, logic low could represent pass and logic high representfail. Similarly, the nonvolatile memory element is set to one state torepresent passage of a test and another to represent failure of thetest.

By locating the circuitry that controls setting of memory elements torepresent test results on the device being tested, the tester equipmentdoes not need to receive values from the device being tested, perform acomparison between test values and received values to determine theoutcome of the test, or determine whether a memory element should be setto store the test result. The tester needs only to transmit test signalsand set signals to the semiconductor device, without receiving anyvalues back from the semiconductor device. Accordingly, the design andconstruction of the test equipment can be simplified considerably.

In one embodiment of the invention, a rule used to determine thesettings of latches and nonvolatile memory elements to representpass/fail status is dependent on the test or test step being performed.That is, for certain tests/test steps a first state would represent passand a second state would represent fail, while for other tests/teststeps the second state would represent pass and the first state wouldrepresent fail. Therefore, a device which had passed all tests would beexpected to have nonvolatile memory elements set in a predeterminedpattern of first and second states. The pattern of first and secondstates corresponding to a known good device is obtained only when thedevice has been properly connected to the test equipment, receivedappropriate test signals and passed all tests.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 is a block diagram of an integrated circuit tester and anintegrated circuit according to an embodiment of the invention;

FIG. 2 is a block diagram of an integrated circuit having a plurality ofsubsections, each including comparator and set circuitry, according toan embodiment of the invention;

FIG. 3 is a block diagram of an integrated circuit having a plurality ofsubsections but a single comparator circuit and set circuit according toa further embodiment of the invention;

FIG. 4 is a flow diagram of the basic operation of an embodiment of theinvention;

FIG. 5 is a flow diagram of the use of an embodiment of the invention inperformance of a burn-in test;

FIG. 6 is a flow diagram of the use of an embodiment of the invention inperformance of a compression test;

FIG. 7 is a block diagram of an electronic system including asemiconductor device having test circuitry according to the presentinvention; and

FIG. 8 is a diagram of a semiconductor wafer having test circuitryconfigured according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A schematic diagram of an embodiment of the present invention is shownin FIG. 1. An integrated circuit device is indicated at 1, and theintegrated circuit device tester used for testing the integrated circuitdevice is indicated at 2.

Integrated Circuit Device Tester

Integrated circuit device tester 2 may be used for testing integratedcircuit device 1. Integrated circuit device tester 2 is configured forsending a test signal on test signal line 21 and a test address signalon test address line 22. The test address signal specifies the addresson integrated circuit device 1 to which the test signal is to be sent.Integrated circuit device tester 2 is also configured for sending a setsignal on set signal line 23 and a set address signal on set addressline 24. Lines 21, 22, 23 and 24 may be single lines or may be busesthat carry multiple signals or bits of data. The set address signalindicates the address of the nonvolatile memory element which is to beset to indicate whether the device has passed or failed a particulartest or test step. Integrated circuit device tester 2 has the capabilityof being programmed to perform multiple test steps, at each test stepdelivering a particular test signal to a particular address or set ofaddresses and subsequently sending a set signal and set address signalto select the nonvolatile memory device address memory which is to storethe results of the test step. The set signal does not cause thenonvolatile memory element to be set directly, but enables setting ofthe nonvolatile memory element by circuitry on integrated circuit device1.

Integrated circuit device tester 2 performs similarly to testerscurrently used in integrated circuit device testing. However, integratedcircuit device tester 2 does not need to perform many of the functionsconventionally performed by prior testers. For example, withoutlimitation, integrated circuit device tester 2 does not need to performthe functions of reading values from integrated circuit device 1,comparing these values with expected values and, based on the results ofthe comparison, generating an instruction for setting a fuse or othernonvolatile memory element on integrated circuit device 1. Thus,integrated circuit device tester 2 used in the practice of the inventioncould be a conventional tester programmed to omit unnecessary functions,but still including the detectors, comparators and other hardware whichmay be used in reading and comparison steps, or it could be a redesignedtester which did not include the detectors, comparators and otherhardware rendered superfluous by the present invention.

Integrated Circuit Device

Integrated circuit device 1 may be a memory device such as a DynamicRandom Access Memory (DRAM), Static Random Access Memory (SRAM), orVideo Random Access Memory (VRAM), FLASH or other nonvolatile memorydevices, a microprocessor, microcontroller, memory controller,Application Specific Integrated Circuit (ASIC) or other device which isto undergo a test sequence. Integrated circuit device 1 may includevarious elements depending upon the type of the device. However, onlythose elements relevant to the functioning of the test circuitry of thepresent invention are shown in the Figures. Referring now to FIG. 1,integrated circuit device 1 includes test circuitry 106 (surrounded by adashed line) which includes send/receive locations 10, comparatorcircuit 11, at least one test latch 12, set logic 13, and nonvolatilememory elements 14. The comparator circuit 11, test latch 12, and setlogic 13 may be included in integrated circuit device 1 in order tocarry out the invention and may not be involved in its regularoperation. However, it is contemplated that circuit elements used in theregular operation of the integrated circuit device may also be used inthe practice of the invention. Test latch 12 is a latch element capableof latching at least two voltage levels (“logic high” or “logic low”).Various types of latches and latch circuits are well known to those ofordinary skill in the art. One example of a latch suitable for use inthe present invention is an S-R NOR latch. Nonvolatile memory elements14 used in the practice of the invention may be existing nonvolatilememory elements already present on integrated circuit device 1 or may beincluded in integrated circuit device 1 specifically for use in theinvention.

Send/receive locations 10 may be memory locations if integrated circuitdevice 1 is a memory device, or they may be inputs and outputs to anintegrated circuit if integrated circuit device 1 is something otherthan a memory device, for example, a microprocessor, microcontroller,memory controller, ASIC, etc. Send/receive locations 10 are employed inthe normal functioning of integrated circuit 1, whereas other componentsof test circuitry 106 are included for testing purposes and may not beused in routine operation of the integrated circuit. Integrated circuitdevice 1 may include multiple send/receive locations 10. At a given teststep, the send/receive location to be tested is selected according tothe test address signal sent on test address line 22 by the integratedcircuit device tester 2. Alternatively, it would be possible to access agiven send/receive location 10 by means of a direct line without the useof addressing. Each send/receive location 10 may contain one bit ormultiple bits (for example, a byte or 8 bits). A test signal is sent tothe selected send/receive location 10 on input line 101, and theresulting output signal is received by comparator circuit 11 oncorresponding output line 102. Input line 101 and output line 102 may beeither the same or separate lines. If send/receive location 10 containsmultiple bits, input line 101 and output line 102 may be either parallelor serial lines. Comparator circuit 11 performs a comparison between thevalue received from the selected send/receive location 10 and the valueexpected to be obtained from a properly functioning device. For example,if the addressed send/receive location 10 is a memory location, thevalue read from the memory location should be the same as the valuewritten to the memory location. If a device other than a memory deviceis being tested, it may be the case that the output value from aparticular address will not be the same as that input to the location.However, if the device is functioning properly, a particular output willalways correspond to a particular input. The comparator circuit 11 maystore (e.g., latch) the current test value for use as the expected valueif a memory device is being tested or it may receive an expected valuesent from integrated circuit device tester 2 separate from the testsignal. As a further alternative, the expected value may be preset inthe device according to a predetermined design rule. In this case,comparator circuit 11 may not truly perform a comparison between theoutput and the expected value. Since the expected value is always thesame, comparator circuit 11 need only be configured so that one outputvalue causes the latch to be set and the other causes it to be unset.This approach would have application primarily in the testing of memorydevices.

Test latch 12 may be set depending on whether or not the output from thesend/receive location matches the expected value. The latch settingpreferably represents the pass or fail status of the test. Test latch 12is connected to set logic 13 via latch signal line 15. When test latch12 is set to a logical high value, set logic 13 receives an enablesignal on latch signal line 15. At the end of a test step, integratedcircuit device tester 2 sends a set signal on set signal line 23 and aset address signal on set address line 24. If both an enable signal anda set signal are received by set logic 13, the nonvolatile memoryelement 14 addressed by the set address signal is set by a signal online 140, thereby providing a permanent record on the integrated circuitdevice 1 of the outcome of the test step. The nonvolatile memoryelements 14 remain unset (i.e., set at its original value) if no enablesignal is received at the time a set signal is received by set logic 13.It would also be possible to configure test latch 12 so that an enablesignal is sent on latch signal line 15 when test latch 12 is set to alogic low value.

Nonvolatile memory elements 14 may include, without limitation, laser orelectrical fuses, antifuses, FLASH memory cells, FERAM memory cells, orother nonvolatile memory elements, which may be set to at least twostates (e.g., blown or unblown in the case of fuses or antifuses,programmed or unprogrammed in the case of FLASH memory cells, or logichigh and logic low for other types of memory elements), one of which mayrepresent a passing test result and one of which may represent a failtest result. Existing semiconductor devices conventionally includeenough nonvolatile memory elements for storing data regarding devicetest results according to the method of the invention without addingadditional elements. However, it is preferred that additional, dedicatednonvolatile memory elements be added. Integrated circuit device 1 mayinclude multiple nonvolatile memory elements. Nonvolatile memoryelements are preferably addressable, being accessed with the use of anaddress signal sent from integrated circuit device tester 2. However, inthe alternative, nonvolatile memory elements could be accessed bydedicated lines or by other means, rather than being addressable.

By first setting test latch 12, and subsequently setting nonvolatilememory element 14 based on the value of test latch 12, the steps ofperforming a comparison and obtaining a test result are separated fromthe step of storing the test result in the nonvolatile memory element14. It may be advantageous to separate these steps because the sameinputs or signal lines may be used in the different steps; thus,separating the steps allows few inputs or lines to be used.

As discussed above, the setting of test latch 12, and subsequently thesetting of a selected nonvolatile memory element 14, represent theresult of a given test step. The relationship between the test resultand the setting of nonvolatile memory element 14 will generally follow apredetermined rule. In the simplest case, the rule will be that for aparticular test result, the latch will always be set to a particularvalue. For example, comparator circuit 11 may be configured to set testlatch 12 to a logical high value if the value on output line 102 matchesthe expected value, i.e., the test step is passed, and a logical lowvalue if the value on output line 102 does not match the expected value,i.e., the test step is failed. Alternatively, comparator circuit 11 maybe configured so that test latch 12 is set to a logical high value ifthe output does not match the expected value, i.e., the test step hasbeen failed, and to a logical low value if the test step is passed. Thevalue to which nonvolatile memory element 14 is set then corresponds tothe value to which test latch 12 is set, so that nonvolatile memoryelement 14 is blown, set or programmed, depending on the type ofnonvolatile memory element when test latch 12 is set high and leftunblown, unset or unprogrammed when test latch 12 is set low.Alternatively, nonvolatile memory element 14 could be blown, set orprogrammed when test latch 12 is set low, and vise versa.

In one embodiment of the invention, comparator circuit 111 and set logic13 may be configured so that the setting of a nonvolatile memory element14 is a function of both the result of the test step and the particulartest step. At certain test steps a nonvolatile memory element 14 may beset to a first state if the test is passed and a second state if thetest is failed, while at other test steps a nonvolatile memory element14 may be set to a second state if the test is passed and a first stateif the test is failed. For example, passing results for sequential teststeps could be represented by a pattern of alternating first and secondstates. In this embodiment of the invention, a device which has passedall tests is expected to have nonvolatile memory elements set in apredetermined pattern of first and second states. The advantage of thisapproach is that the pattern of first and second states corresponding toa known good device is likely to be obtained only when the device hasbeen properly connected to the test equipment, received appropriate testsignals, and passed all tests. In contrast, if pass results arerepresented with a single nonvolatile memory setting, false pass resultsmay be obtained if a device has all nonvolatile memory locations set tothe same value prior to testing and the original settings are notchanged during testing because the device is not properly connected tothe semiconductor device.

Although it is preferred to include the step of setting a latchintermediate the steps of determining a test result and storing the testresult in a nonvolatile memory element for the reasons noted previously,the concept of storing test results as a function of test step and testresult could be applied in a system in which test results were storeddirectly in nonvolatile memory elements without the intermediate step ofstoring the results first in a latch. The general concept of storingtest results in nonvolatile memory elements without intermediate storagein a latch is already known in the prior art.

As described above, the results of each test step may be represented inthe setting of a selected nonvolatile memory element 14 according to apredetermined rule. Either one or both of comparator circuit 11 or setlogic 13 may include circuitry which implements said predetermined rule.

In the embodiment of the invention depicted in FIG. 1, integratedcircuit device 1 includes a single test latch 12. At each test step,test latch 12 temporarily stores the result of the current test stepand, as described above, enables the setting of a nonvolatile memoryelement 14 to permanently store the result of the test step. Thus, testlatch 12 stores the result of one test step at a time, but stores theresults of multiple test steps in sequence. It is contemplated, however,that in other embodiments of the invention, integrated circuit device 1may include test circuitry 106 (surrounded by dashed line) which isdivided into a plurality of subsections or quadrants 1 a, 1 b, 1 c, and1 d, as depicted in FIG. 2. Each subsection may include a plurality ofsend/receive locations 10 a, 10 b, 10 c and 10 d accessed bycorresponding input lines 101 a, 101 b, 101 c and 101 d and output lines102 a, 102 b, 102 c, and 102 d. Each quadrant also includes a comparatorcircuit 11 a, 11 b, 11 c, or 11 d; a test latch 12 a, 12 b, 12 c, or 12d; a latch signal line 15 a, 15 b, 15 c or 15 d communicating with setlogic 13 a, 13 b, 13 c or 13 d. Each subsection may include a pluralityof nonvolatile memory elements 14 a, 14 b, 14 c or 14 d set by lines 140a, 140 b, 140 c and 140 d, respectively. Each test latch 12 a, 12 b, 12c or 12 d stores the results of the current test step for a particularsubsection. Test, test address, set and set address signals are sent onlines 21, 22, 23 and 24 as noted previously. Thus each subsection may betested independently. Although four subsections are depicted in FIG. 2,this is merely exemplary, and the invention may include a larger orsmaller number of subsections. If multiple test latches are used, eachlatch may be independently addressable or may be accessed by means of adedicated line.

In yet another alternative embodiment of the invention, as depicted inFIG. 3, test circuitry 106 (enclosed by dashed line) includes aplurality of subsections 310 a, 310 b, 310 c, 310 d (four are shownhere) each containing multiple send/receive locations 10 a, 10 b, 10 cor 10 d, which are accessed by input lines 101 a, 101 b, 101 c and 101d, respectively; output lines 102 a, 102 b, 102 c and 102 d,respectively; a single comparator circuit 311; test latch 312; latchsignal line 315; and set logic 313. This permits a comparison to be madebetween the values received from send/receive locations in the differentsubsections of the device. Multiple nonvolatile memory elements 14 arealso included accessible by lines 140. Test, test address, set and setaddress signals are sent on lines 21, 22, 23 and 24, respectively.

The different embodiments of the invention are particularly suited fordifferent types of device testing, as will be described hereinbelow. Itwill be appreciated that the embodiments of the invention depicted inFIGS. 1, 2 and 3 may be implemented on a single semiconductor device,with the send/receive locations 10 connected to one or more embodimentsof the comparator circuitry 11, 11 a, 11 b, . . . , 311 a, 311 b, . . ., etc., in order to facilitate testing of the integrated circuit device1 in a variety of test modes.

In yet another embodiment of the invention, multiple latches may beprovided on integrated circuit device 1, or on each subsection ofintegrated circuit device 1, so that results of multiple test steps maybe stored in latches prior to being stored in nonvolatile memoryelements. Thus, multiple test steps may be presented in sequence, andthe step of storing the test results in nonvolatile memory elements maybe carried out after a sequence of test steps has been presented, ratherthan after each test step. Each latch may be independently addressableor may be accessed by means of a dedicated line.

Testing Procedure

During testing of an integrated circuit device 1, a variety of testsignals may be sent to the device in sequence by the integrated circuitdevice tester 2. Values received or read from the device are comparedwith expected values. The results of the comparisons are ultimatelystored on the device in multiple nonvolatile memory elements. Eachnonvolatile memory element may represent the results of a particulartest or test step. Nonvolatile memory elements may be configured torepresent different time points or read points in a test sequence or torepresent test results for particular regions of the integrated circuitdevice. An advantage of storing test results in nonvolatile memoryelements on the device is that the nonvolatile memory elements can bechecked later to determine results of tests as well as whether a testwas carried out properly; the device thus carries its own test history.

In some cases, whether the result obtained at a particular test step maydetermine whether a subsequent test step should be carried out.Therefore, in such cases it will be necessary for test equipment, suchas integrated circuit device tester 2, to read test results stored onintegrated circuit device 1 so that an appropriate subsequent test stepcan be determined.

Prior art integrated circuit device testers include the intelligence fordetermining whether to set a nonvolatile memory element on theintegrated circuit device by evaluating the results of tests performedon the device. With the present invention, the device being testedincludes the intelligence to determine whether to set a givennonvolatile memory element to represent test results. The tester sends aset signal and a set address indicating the address of the nonvolatilememory element associated with the current test step for each test step.However, the nonvolatile memory element is set only if the set signal ispresent and the latch storing the result of the comparison indicatesthat the nonvolatile memory element should be set. The followingexamples describe the process by which test steps are delivered, testresults are determined, and storage of test results on the semiconductordevice in nonvolatile memory elements.

EXAMPLE 1 General Testing

A flow diagram for the general test procedure used with the embodimentof the invention in FIG. 1 is shown in FIG. 4. This procedure may alsobe used for testing individual subsections of a device as in FIG. 2. Inthis example, a total number of R test steps are applied, with rrepresenting the current test step. N is the total number ofsend/receive locations tested, with n representing the currentsend/receive location. The general testing procedure begins at 401 andis carried out for values of r=1 to R (step 402) and n=1 to N (step403). The integrated circuit device tester sends the address forsend/receive location n and test value r which is then stored insend/receive location n of the semiconductor device 1 (step 404). Thecomparator circuit for the semiconductor device or semiconductor devicesubsection then performs a comparison between the value received (read)from send/receive location n and the value expected to be obtained fromthat location in a properly functioning device (step 405). If the valuesdo not match, the test latch is set appropriately (step 406). If thevalues do not match, control goes directly to step 407, in which theintegrated circuit device tester sends a set signal and a set addresssignal to the semiconductor device. At step 408, set logic on thesemiconductor device determines whether a set signal is present and thetest latch has been set. If so, nonvolatile memory device r,n is set atstep 409. If not, control goes directly to step 410, in which the devicetester checks whether the send/receive location being tested is the lastsend/receive location. If not, control returns to step 403 and thetester delivers the test step to the next send/receive location. If atstep 410 it is determined that the last send/receive location has beenreached (that is, all send/receive locations have been tested with thecurrent test step), the tester checks whether the last test step hasbeen reached (step 411). If not, control returns to step 402 and thenext test step is delivered. If the last test step has been delivered,testing is ended (step 412). It is preferred that a separate nonvolatilememory element is used at step 409 to store the result of each teststep. At each test step, a single latch is used to store a valueindicating whether setting of the nonvolatile memory element associatedwith that test step is to be enabled. On subsequent test steps, the samelatch may be used to enable setting of different nonvolatile memoryelements associated with the different test steps. There may be a singlelatch for each device for storing test step results, as shown in FIG. 1.Alternatively, it may be desirable to test several sections of asemiconductor device (e.g., subarrays of memory) separately and storetest results in a separate latch for each section, in which case thesemiconductor device as a whole would include at least as many latchesas there were sections, as shown in FIG. 2. Although the flow diagramfor the standard test in FIG. 4 shows the tester cycling through allsend/receive locations for a given test step before moving on to thenext test step, it may also be preferable to cycle through all teststeps at a particular send/receive location before moving to the nextsend/receive location, that is, to place the loop beginning at step 403outside the loop beginning at step 402.

EXAMPLE 2 Burn-In Testing

A flow diagram for burn-in testing is provided in FIG. 5. This testprocedure may be used with a device as depicted in FIG. 1, or subsectionof a device as depicted in FIG. 2. During burn-in testing, a particulardata value is written repeatedly to a particular send/receive location,typically under extreme conditions of temperature, voltage, timing,etc., in an effort to cause the failure of a device having some flawthat would cause it to fail early in its life cycle. Data are read froma given send/receive location at each repetition or at specifiedintervals in order to determine if and when failure occurs. Multiplenonvolatile memory elements may be used to store the pass/failinformation for the different read points, with each nonvolatile memoryelement representing one read point. Read points may be used torepresent specific time intervals throughout a burn in test such that,for example, a nonvolatile memory element is set after each hour ofburn-in testing. Nonvolatile memory elements may also be used to storethe number of the current read point, so that a record of the number ofrepetitions is stored on the device at all times during testing. In FIG.5, R represents the total number of test steps, r the current test step,N represents the total number of send/receive locations tested, n thecurrent send/receive location, P the total number of repetitions, and pthe number of the current repetition. The burn-in test procedure beginsat step 501, and is carried out for values of r=1 to R (step 502), n=1to N (step 503), and p=1 to P (step 504). At each repetition p, thetester sends a test value r to send/receive location n (step 505). Thesemiconductor device compares the test value with the value read fromsend/receive location n (step 506). If a mismatch occurs, indicating afailure, the test latch is set at step 507. If the values match, step507 is bypassed. The tester next sends a set signal and a set addresscorresponding to the nonvolatile memory elements designated to store thetest result for the current repetition p (step 508). If a set signal ispresent and the test latch has been set (step 509), the semiconductordevice causes the selected nonvolatile memory element to be set (step510). Control returns to step 504 from step 511 until a total of Prepetitions of the test signal have been delivered. Testing continuesuntil all send/receive locations have been tested (step 512) and alltest sequences have been delivered (513).

EXAMPLE 3 Compression Testing

Compression testing is used to shorten test times by simultaneouslytesting several identical subsections of a semiconductor device, orseveral regions on different devices of the same type. The block diagramof FIG. 3 depicts a semiconductor device having multiple subsections(four in this example, but any number greater than one could be used)and comparator circuit and set logic configured for use in compressiontesting. The same data values are simultaneously written to multiplesubsections of the device (for example, to memory cells in multiplesubsections of the device) and then data are read back from eachsubsection and values read from all subsections are compared. Matchingvalues indicate that the test was passed. If a mismatch is detected,this indicates that some of the tested areas are not functioningproperly and the test has been failed. If the test has been failed, alatch is set to enable or disable setting of a selected nonvolatilememory element. A flow diagram for compression testing is given in FIG.6. R represents the total number of test steps, r the current test step,N the total number of send/receive locations tested in each subsectionof the semiconductor device, and n₁, n₂, n₃ . . . n_(m) the currentsend/receive location in subsections 1 . . . m of the semiconductordevice. In FIG. 6, a semiconductor device with four subsections isdepicted, so m=4, but it will be appreciated that this is merelyexemplary, and a larger or smaller number of subsections could be usedin the practice of the invention. Naturally, at least two subsectionsmust be present in order to perform a comparison. The test procedurebegins at step 601. The test procedure is carried out for values of r=1to R (step 602) and n=1 to N (step 603). At step 604, test value r issimultaneously sent to send/receive locations n₁, n₂, n₃ . . . n_(m). Atstep 605, the semiconductor device compares the values received fromsend/receive locations n₁, n₂, n₃ . . . n_(m). If a mismatch isdetected, a test latch is set (step 606). If all values match, step 606is bypassed. The tester then sends a set signal and an address signalfor nonvolatile memory element r,n (step 607). If a set signal ispresent and the test latch is set (step 608), the semiconductor devicesets nonvolatile memory element r,n (step 609). Control returns to step603 from step 610 until a total of N send/receive locations have beentested in each subsection with test step r. Testing continues until alltest steps have been delivered (611).

FIG. 7 shows a block diagram of an electronic system 700 which includescomponents having one or more test circuits 106 configured according toone or more embodiments of the present invention. The electronic system700 includes a processor 704 for performing various computing functions,such as executing specific software to perform specific calculations ortasks. Additionally, the electronic system 700 includes one or moreinput devices 708, such as a keyboard or mouse, coupled to the processor704 to allow an operator to interface with the electronic system 700.The electronic system 700 also includes one or more output devices 710coupled to the processor 704, such output devices including but notlimited to a printer, a video terminal or a network connection. One ormore data storage devices 712 are also conventionally coupled to theprocessor 704 to store or retrieve data from external storage media (notshown). Examples of conventional storage devices 712 include hard andfloppy disks, tape cassettes, compact disks and optical memory. Theprocessor 704 is also conventionally coupled to a cache memory 714,which is usually static random access memory (“SRAM”), and to DRAM 702.It will be understood, however, that the test circuit 106 configuredaccording to one or more of the embodiments of the present invention maybe incorporated into any one of the cache, DRAM, input, output, storageand processor devices 714, 702, 708, 710, 712 and 704.

As shown in FIG. 8, test circuit 106 may be fabricated on the surface ofa semiconductor wafer 816 of silicon, gallium arsenide, or indiumphosphide in accordance with one or more embodiments of the presentinvention. One of ordinary skill in the art will understand how to adaptsuch design for a specific chip architecture or semiconductorfabrication process. Of course, it should be understood that the testcircuit 106 may be fabricated on semiconductor substrates other than awafer, such as a Silicon-on-Insulator (SOI) substrate, aSilicon-on-Glass (SOG) substrate, a Silicon-on-Sapphire (SOS) substrate,or other semiconductor material layers on supporting substrates.

As will be clear to one of ordinary skill in the art, the principles ofthe present invention may be used in conjunction with any number of thevarious semiconductor test methods known in the art and is not limitedto those test methods described herein, or to the testing of memorydevices. By including at least one latch circuit within a semiconductordevice to indicate whether a nonvolatile memory element should beinitiated, testing devices may be simplified. Additionally, by storingpassing test result data as a mixed code of two different states ratherthan merely as a series of entirely the first state or the second state,the success of a series of tests may more accurately be determined.

While the present invention has been described and illustrated in termsof certain specific embodiments, those of ordinary skill in the art willunderstand and appreciate that it is not so limited. Additions to,deletions from and modifications to these specific embodiments may beeffected without departing from the scope of the invention as defined bythe claims. Furthermore, features and elements from one specificembodiment may be likewise applied to another embodiment withoutdeparting from the scope of the invention as defined herein.

1. An integrated circuit comprising: a location configured to receive atest signal and provide the test signal to an input of a logic function;and comparator circuitry coupled to both an output of the logic functionand an expected signal and configured to set a state in a nonvolatilememory element in response to the output and the expected signal.
 2. Theintegrated circuit of claim 1, wherein the nonvolatile memory elementcomprises a fuse.
 3. The integrated circuit of claim 1, wherein thenonvolatile memory element comprises an antifuse.
 4. The integratedcircuit of claim 1, wherein the nonvolatile memory element comprises aFLASH memory cell.
 5. The integrated circuit of claim 1, wherein theintegrated circuit is a memory device.
 6. The integrated circuit ofclaim 5, wherein the memory device is selected from a group consistingof a DRAM, a SRAM, a VRAM and a FLASH memory.
 7. The integrated circuitof claim 1, wherein the integrated circuit is a microprocessor.
 8. Theintegrated circuit of claim 1, wherein the integrated circuit is amicrocontroller.
 9. The integrated circuit of claim 1, wherein theintegrated circuit is a memory controller.
 10. The integrated circuit ofclaim 1, wherein the integrated circuit is an application specificintegrated circuit (ASIC).
 11. A memory device comprising: at least onememory location, the at least one memory location configured to receivea test signal and provide the test signal to an input of a logicfunction; and comparator circuitry coupled to both an output of thelogic function and an expected signal and configured to set a state in anonvolatile memory element in response to the output and the expectedsignal.
 12. The memory device of claim 11, wherein the nonvolatilememory element is a fuse.
 13. The memory device of claim 11, wherein thenonvolatile memory element is an antifuse.
 14. The memory device ofclaim 11, wherein the nonvolatile memory element is a FLASH memory cell.15. An electronic system comprising: at least one processor; at leastone input device; at least one output device; at least one storagedevice; a test circuit incorporated into at least one device of the atleast one processor, the at least one input device, the at least oneoutput device, and the at least one storage device, the test circuitcomprising: a location configured to receive a test signal and providethe test signal to an input of a logic function; and comparatorcircuitry coupled to both an output of the logic function and anexpected signal and configured to set a state in a nonvolatile memoryelement in response to the output and the expected signal.